The present invention relates to a semiconductor integrated circuit having as short a channel length as possible, capable of being integrated at a high density, and particularly employing an insulated-gate transistor of high drivability (driving capability) and high operation speed.
Efforts have been made to shorten the channel length and achieve a higher density in insulated-gate field-effect transistor (hereinafter referred to as a "MOSFET") for higher performance.
MOSFETs having shorter channel lengths are normally designed on the basis of the scaling theory. As described in detail in Japanese Patent Application No. 57-113709 filed on June 29, 1982, entitled "Semiconductor Integrated Circuit", shortening the channel length based on the scaling theory has suffered drawbacks in that since the concentration of impurities in the channel is increased as the channel length is shortened, the mobility of carriers travelling through the channel is lowered, and carriers induced directly below a gate insulating film are distributed to a depth of at most about 100.ANG. or smaller. Therefore, the effective carrier mobility is further lowered resulting in a smaller transconductance. The input capacitance of the gate is increased, and characteristics are not so improved as expected of the shortened channel length. The drain breakdown voltage is inevitably reduced with increasing the channel impurity concentration. Another shortcoming is that since a voltage applied to the drain is concentrated on the end of the channel close to the drain, its electric field intensity is increased to produce a greater hot-electron effect, resulting in a wide variation in a threshold voltage.
To overcome the foregoing drawbacks, there have been proposed insulated-gate static induction transistors (hereinafter referred to as "MOSSIT") in which the concentration of impurities in the channel in which carriers travel is sufficiently low, induced carriers distributed not only just under the gate insulating film but sufficiently deep into the interior, thus the carrier mobility and the transconductance are large, the gate input capacitance is small, the operation speed is higher as the channel length is shorter, the power consumption is small, and the drain breakdown voltage is large. Such MOSSITs are disclosed in Japanese Patent Application No. 54-108377 entitled "Insulated-Gate Transistor and Integrated Circuit", Japanese Patent Application No. 54-115491 entitled "Semiconductor Memory", Japanese Patent Application No. 57-113709 entitled "Semiconductor Integrated Circuit", and Japanese Patent Application No. 57-161980 entitled "Semiconductor Integrated Circuit". One example of the MOSSIT is shown in FIG. 1 of the accompanying drawings. Designated in FIG. 1 at 11 is an electrode, 12 a p.sup.+ substrate, 13 a high-resistivity p.sup.- region, 14, 15 n.sup. + region, 16, 17 layers of MoSi.sub.2, WSi.sub.2, TaSi.sub.2, TiSi.sub.2, Pd.sub.2 Si, 18, 19 electrodes of Al, AlSi.sub.2, AlCu, 20 a gate insulating film or gate oxide film, 21 a gate electrode, 22 isolation regions, 23 a PSG film, and 24 a passivation PSG or nitride (Si.sub.3 N.sub.4) film.
The region 13 is a high-resistivity region with a low impurity concentration of 1.times.10.sup.15 cm.sup.-3 or below, preferably 1.times.10.sup.14 cm.sup.-3 or below. Normally-off characteristics of this MOS transistor is not achieved by increasing the impurity concentration in the channel as with conventional MOSFETs, but by a diffusion potential of the p.sup.+ region of the substrate with respect to the n.sup.+ source region and a diffusion potential of the gate electrode material with respect to the n.sup.+ source region. Stated otherwise, a potential barrier is created in the channel by the diffusion potentials of the p.sup.+ substrate and the gate electrode.
It is preferable that the gate electrode material have a high diffusion potential relative to the n.sup.+ source region. For example, a portion of the gate electrode which is adjacent to the gate insulating film will have a high diffusion potential if made of p.sup.+ polysilicon. Where the resistance of the gate electrode is too high with only p.sup.+ polysilicon used, a layer of silicide or a metal electrode should be placed on the gate electrode. For example, when boron-doped silicon-rich molybdenum silicide is deposited as by RF bias sputtering technics and followed by thermal treatment, p.sup.+ polysilicon is precipitated in a portion adjacent to the gate insulating film with MoSi.sub.2 formed thereon. The gate electrode may be of Al, AlSi.sub.2, or AlCu. The gate electrode of Al has a diffusion potential of about 0.7 V relative to the n.sup.+ region. Other metals such for example as Mo, W or metal silicides such for example as MoSi.sub.2, WSi.sub.2, TaSi.sub.2, TiSi.sub.2, Pd.sub.2 Si may also be used.
The region 13 shown in FIG. 1 is a p.sup.- region. If the impurity concentration is about 10.sup.14 cm.sup.-3 or below, then the potential distribution in the channel remains substantially unchanged even with the n.sup.- region. Let the depth of the p.sup.- region be expressed by D and the effective channel length by L.sub.eff, the normally-off characteristics is sufficiently held up to a range indicated by:
L.sub.eff /D.gtoreq.1
in the construction of FIG. 1 under the condition that no bias voltage is applied to the substrate.
FIG. 2 shows a distribution of electron concentration induced in a semiconductor below a gate oxide film when a voltage of 3 V is applied to a MOS diode in which the gate oxide film has a thickness of 200.ANG.. Naturally, electrons are distributed more deeply in the substrate as the impurity concentration in the substrate is lower. The potential distribution at this time is illustrated in FIG. 3.
Now, a voltage of a waveform having a unit step function as shown in FIG. 4(a) is applied to the gate of the MOS transistor constructed as shown in FIG. 1. It is assumed that a power supply for generating such a voltage has a sufficiently small internal resistance and can supply a sufficient current, and the resistivity of the p.sup.+ substrate 12 is sufficiently small. At the moment the unit step voltage is applied, a potential distribution from the gate electrode to the p.sup.+ substrate is as shown in FIG. 4(b) in which a negative voltage is shown as being higher since the potential with respect to electrons is illustrated. Designated in FIG. 4(b) at V.sub.g is a voltage applied to the gate, V.sub.bi1 a diffusion potential of the gate electrode 21 to the n.sup.+ source region 14, and V.sub.bi2 a diffusion potential of the p.sup.+ substrate 12 to the n.sup.+ source region 14. Indicated by the horizontal dotted line in FIG. 4(b) is a Fermi level of the n.sup.+ source region. A voltage V.sub.ox across the gate oxide film and a voltage V.sub.s applied to the semiconductor are given respectively by: ##EQU1## A surface potential .phi..sub.s directly below the gate insulating film is given by: EQU .phi..sub.s =V.sub.bi1 +V.sub.ox .div.V.sub.g ( 3)
where .epsilon..sub.ox and .epsilon..sub.s are the dielectric constants of the gate insulating film and the semiconductor, and T.sub.ox is the thickness of the gate insulating film. If .phi..sub.s &lt;0, then a potential region with its potential lower than that of the source extends from the surface to x as shown in FIG. 4(b), and a large amount of electrons are momentarily injected from the source into the channel so that a large current flows. When electrons are injected from the source into the channel, the potential distribution is changed to one similar to that shown in FIG. 3.
At any rate, with a bulk MOS or epitaxial MOS in which the channel region as shown on FIG. 1 is contiguous to the substrate, the substrate is kept at a constant voltage (which is the same as that of the source in FIG. 4(b)), and the entire channel regions prevented from being at a potential lower than the source potential. Therefore, no large instantaneous current flows, and there is little effect of highly increasing the driving capability at the time of high-speed operation.